1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices. More specifically, this invention relates to the manufacture of high performance semiconductor devices having reduced channel length transistors.
2. Discussion of the Related Art
In order to achieve higher operating frequencies and higher transconductance, a short gate channel length is necessary. Shortening the channel length inherently increases the switching speed of the transistor because charge carriers such as electrons have a shorter distance to travel between the source and drain of the transistor. Since the charge carriers travel a shorter distance, the charge carriers are able to complete the journey in a shorter period of time.
Typically a photolithography process is used to pattern the polysilicon gate. After a global deposition of a layer of polysilicon over the semi-processed substrate, a layer of photoresist is then coated over the polycrystalline silicon. The radiation (illumination) from a radiation source is used to transfer the patterns from a reticule onto the wafer. The radiation excites the photosensitive resins and subsequent processes remove the unexcited photoresist to form patterns on top of the polysilicon layer. A subtractive etch process then replicates the photoresist patterns to form polysilicon gates.
Because the demand for higher and higher speed devices is continuing, the requirement for smaller transistors has outstripped the ability of available illumination or radiation sources to reliably process the transistors in mass quantities with the requisite quality. Typically, a deep ultra-violet source having a wavelength of 250 nanometers or smaller is used for the quarter micron process. The minimum printable feature size is within the optical threshold of the deep ultra-violet illumination source. However, at these transistor dimensions, the speed generated is far less than that desired. The minimum requirement for leading edge microprocessors demands a gate length near or below that available from the next generation of radiation sources having a wavelength of approximately 193 nanometers and less. However, because this wavelength is in the region of x-ray radiation, and because x-ray radiation is difficult to control, more advanced techniques utilizing more conventional radiation sources are required to continue the downward scaling of transistor dimensions.
One advanced technique is to reduce the photoresist pattern prior to the etch process. As is known in the field of semiconductor manufacturing, an etch process inevitably leaves a positive (outward) sloped structural profile. This is caused by the phenomenon known as the aspect ratio etch dependency phenomenon in which polymer buildup on sidewalls of structures produce a structure that has a larger base. Since the switching of the transistor is accomplished at the base of the polysilicon (gate) structure, it is important that the base of the polysilicon gate is kept at a minimum. However, the performance gain from this technique is less than optimal for a given critical dimension.
Therefore, what is needed is a technique to exploit currently available radiation sources, materials and equipment that can be used in well understood processes to continue the downward scaling of transistor dimensions.
According to the present invention, the foregoing and other objects and advantages are achieved by forming spacers on each side of trenches that define transistor channels that are formed in a semiconductor substrate in the semiconductor device. The trenches are formed in a stack of materials including a layer of dielectric, a layer of a high K dielectric material and a layer of material that acts as a polish stop layer. The spacers are formed with a dimension between the spacers that is less than a dimension available from photolithography systems currently available. A layer of gate oxide and a polysilicon gate are formed within the dimension resulting in transistors having a channel length less than that available from standard photolithographic methods of forming gates and channels.
In accordance with an aspect of the invention, PLDD regions and NLDD regions are formed in the respective n-well regions and p-well regions. Standard sidewall spacers are formed on the polysilicon gates and source and drain regions are formed in the respective n-well regions and p-well regions.
In accordance with another aspect of the invention, a layer of an etch stop material is formed on the layer of dielectric before the layer of high K dielectric material, the layer of material formed on the layer of high K dielectric material.
In accordance with still another aspect of the invention, the PLDD regions and NLDD regions are formed in the respective n-well regions and p-well regions by implanting ions at an angle through a PLDD mask and an NLDD mask, respectively. Source and drain regions in the respective n-well regions and p-well regions are formed by implanting ions through the same PLDD mask and NLDD mask.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described embodiments of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.